/* Copyright Statement:
*
* This software/firmware and related documentation ("MediaTek Software") are
* protected under relevant copyright laws. The information contained herein
* is confidential and proprietary to MediaTek Inc. and/or its licensors.
* Without the prior written permission of MediaTek inc. and/or its licensors,
* any reproduction, modification, use or disclosure of MediaTek Software,
* and information contained herein, in whole or in part, shall be strictly prohibited.
*/
/* MediaTek Inc. (C) 2015. All rights reserved.
*
* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
*/

#ifndef _DDP_REG_OVL_H_
#define _DDP_REG_OVL_H_

#include "hw/DISP_OVL_c_header.h"

#define DISP_REG_OVL_STA						DISP_OVL0_OVL_STA
	#define STA_FLD_RUN								OVL_STA_FLD_OVL_RUN
	#define STA_FLD_RDMA0_IDLE						OVL_STA_FLD_RDMA0_IDLE
	#define STA_FLD_RDMA1_IDLE						OVL_STA_FLD_RDMA1_IDLE
	#define STA_FLD_RDMA2_IDLE						OVL_STA_FLD_RDMA2_IDLE
	#define STA_FLD_RDMA3_IDLE						OVL_STA_FLD_RDMA3_IDLE

#define DISP_REG_OVL_INTEN						DISP_OVL0_OVL_INTEN
	#define INTEN_FLD_REG_CMT_INTEN					OVL_INTEN_FLD_OVL_REG_CMT_INTEN
	#define INTEN_FLD_FME_CPL_INTEN					OVL_INTEN_FLD_OVL_FME_CPL_INTEN
	#define INTEN_FLD_FME_UND_INTEN					OVL_INTEN_FLD_OVL_FME_UND_INTEN
	#define INTEN_FLD_FME_SWRST_DONE_INTEN			OVL_INTEN_FLD_OVL_FME_SWRST_DONE_INTEN
	#define INTEN_FLD_FME_HWRST_DONE_INTEN			OVL_INTEN_FLD_OVL_FME_HWRST_DONE_INTEN
	#define INTEN_FLD_RDMA0_EOF_ABNORMAL_INTEN		OVL_INTEN_FLD_RDMA0_EOF_ABNORMAL_INTEN
	#define INTEN_FLD_RDMA1_EOF_ABNORMAL_INTEN		OVL_INTEN_FLD_RDMA1_EOF_ABNORMAL_INTEN
	#define INTEN_FLD_RDMA2_EOF_ABNORMAL_INTEN		OVL_INTEN_FLD_RDMA2_EOF_ABNORMAL_INTEN
	#define INTEN_FLD_RDMA3_EOF_ABNORMAL_INTEN		OVL_INTEN_FLD_RDMA3_EOF_ABNORMAL_INTEN
	#define INTEN_FLD_RDMA0_SMI_UNDERFLOW_INTEN 	OVL_INTEN_FLD_RDMA0_SMI_UNDERFLOW_INTEN
	#define INTEN_FLD_RDMA1_SMI_UNDERFLOW_INTEN		OVL_INTEN_FLD_RDMA1_SMI_UNDERFLOW_INTEN
	#define INTEN_FLD_RDMA2_SMI_UNDERFLOW_INTEN		OVL_INTEN_FLD_RDMA2_SMI_UNDERFLOW_INTEN
	#define INTEN_FLD_RDMA3_SMI_UNDERFLOW_INTEN		OVL_INTEN_FLD_RDMA3_SMI_UNDERFLOW_INTEN
	#define INTEN_FLD_ABNORMAL_SOF					OVL_INTEN_FLD_ABNORMAL_SOF_INTEN
	#define INTEN_FLD_START_INTEN					OVL_INTEN_FLD_OVL_START_INTEN


#define DISP_REG_OVL_INTSTA						DISP_OVL0_OVL_INTSTA
	#define INTSTA_FLD_REG_CMT_INTSTA				OVL_INTSTA_FLD_OVL_REG_CMT_INTSTA
	#define INTSTA_FLD_FME_CPL_INTSTA				OVL_INTSTA_FLD_OVL_FME_CPL_INTSTA
	#define INTSTA_FLD_FME_UND_INTSTA				OVL_INTSTA_FLD_OVL_FME_UND_INTSTA
	#define INTSTA_FLD_FME_SWRST_DONE_INTSTA		OVL_INTSTA_FLD_OVL_FME_SWRST_DONE_INTSTA
	#define INTSTA_FLD_FME_HWRST_DONE_INTSTA		OVL_INTSTA_FLD_OVL_FME_HWRST_DONE_INTSTA
	#define INTSTA_FLD_RDMA0_EOF_ABNORMAL_INTSTA	OVL_INTSTA_FLD_RDMA0_EOF_ABNORMAL_INTSTA
	#define INTSTA_FLD_RDMA1_EOF_ABNORMAL_INTSTA	OVL_INTSTA_FLD_RDMA1_EOF_ABNORMAL_INTSTA
	#define INTSTA_FLD_RDMA2_EOF_ABNORMAL_INTSTA	OVL_INTSTA_FLD_RDMA2_EOF_ABNORMAL_INTSTA
	#define INTSTA_FLD_RDMA3_EOF_ABNORMAL_INTSTA	OVL_INTSTA_FLD_RDMA3_EOF_ABNORMAL_INTSTA
	#define INTSTA_FLD_RDMA0_SMI_UNDERFLOW_INTSTA	OVL_INTSTA_FLD_RDMA0_SMI_UNDERFLOW_INTSTA
	#define INTSTA_FLD_RDMA1_SMI_UNDERFLOW_INTSTA	OVL_INTSTA_FLD_RDMA1_SMI_UNDERFLOW_INTSTA
	#define INTSTA_FLD_RDMA2_SMI_UNDERFLOW_INTSTA	OVL_INTSTA_FLD_RDMA2_SMI_UNDERFLOW_INTSTA
	#define INTSTA_FLD_RDMA3_SMI_UNDERFLOW_INTSTA	OVL_INTSTA_FLD_RDMA3_SMI_UNDERFLOW_INTSTA
	#define INTSTA_FLD_ABNORMAL_SOF					OVL_INTSTA_FLD_ABNORMAL_SOF_INTSTA)
	#define INTSTA_FLD_START_INTEN					OVL_INTSTA_FLD_OVL_START_INTSTA


#define DISP_REG_OVL_EN							DISP_OVL0_OVL_EN
	#define EN_FLD_OVL_EN							OVL_EN_FLD_OVL_EN
	#define EN_FLD_OVL_CKON							OVL_EN_FLD_HG_FOVL_CK_ON
	#define EN_FLD_SMI_CKON							OVL_EN_FLD_HG_FSMI_CK_ON
	#define EN_FLD_IGNORE_ABN_SOF					OVL_EN_FLD_IGNORE_ABNORMAL_SOF
	#define EN_FLD_BLOCK_EXT_ULTRA 					OVL_EN_FLD_BLOCK_EXT_ULTRA
	#define EN_FLD_BLOCK_EXT_PREULTRA				OVL_EN_FLD_BLOCK_EXT_PREULTRA


#define DISP_REG_OVL_TRIG						DISP_OVL0_OVL_TRIG
	#define TRIG_FLD_SW_TRIG						OVL_TRIG_FLD_OVL_SW_TRIG

#define DISP_REG_OVL_RST						DISP_OVL0_OVL_RST
#define DISP_REG_OVL_ROI_SIZE					DISP_OVL0_OVL_ROI_SIZE
	#define ROI_SIZE_FLD_ROI_W						OVL_ROI_SIZE_FLD_ROI_W
	#define ROI_SIZE_FLD_ROI_H						OVL_ROI_SIZE_FLD_ROI_H

#define DISP_REG_OVL_DATAPATH_CON				DISP_OVL0_OVL_DATAPATH_CON
	#define DATAPATH_CON_FLD_LAYER_SMI_ID_EN		OVL_DATAPATH_CON_FLD_LAYER_SMI_ID_EN
	#define DATAPATH_CON_FLD_RANDOM_BGCLR_EN		OVL_DATAPATH_CON_FLD_OVL_RANDOM_BGCLR_EN
	#define DATAPATH_CON_FLD_BGCLR_IN_SEL			OVL_DATAPATH_CON_FLD_BGCLR_IN_SEL
	#define DATAPATH_CON_FLD_L0_GPU_MODE			OVL_DATAPATH_CON_FLD_L0_GPU_MODE
	#define DATAPATH_CON_FLD_L1_GPU_MODE			OVL_DATAPATH_CON_FLD_L1_GPU_MODE
	#define DATAPATH_CON_FLD_L2_GPU_MODE			OVL_DATAPATH_CON_FLD_L2_GPU_MODE
	#define DATAPATH_CON_FLD_L3_GPU_MODE			OVL_DATAPATH_CON_FLD_L3_GPU_MODE
	#define DATAPATH_CON_FLD_ADOBE_MODE				OVL_DATAPATH_CON_FLD_ADOBE_MODE
	#define DATAPATH_CON_FLD_ADOBE_LAYER			OVL_DATAPATH_CON_FLD_ADOBE_LAYER
	#define DATAPATH_CON_FLD_OVL_GAMMA_OUT			OVL_DATAPATH_CON_FLD_OVL_GAMMA_OUT
	#define DATAPATH_CON_FLD_PQ_OUT_SEL				OVL_DATAPATH_CON_FLD_PQ_OUT_SEL
	#define DATAPATH_CON_FLD_RDMA0_OUT_SEL			OVL_DATAPATH_CON_FLD_RDMA0_OUT_SEL
	#define DATAPATH_CON_FLD_RDMA1_OUT_SEL			OVL_DATAPATH_CON_FLD_RDMA1_OUT_SEL
	#define DATAPATH_CON_FLD_RDMA2_OUT_SEL			OVL_DATAPATH_CON_FLD_RDMA2_OUT_SEL
	#define DATAPATH_CON_FLD_RDMA3_OUT_SEL			OVL_DATAPATH_CON_FLD_RDMA3_OUT_SEL
	#define DATAPATH_CON_FLD_GCLAST_EN				OVL_DATAPATH_CON_FLD_GCLAST_EN
	#define DATAPATH_CON_FLD_OUTPUT_CLAMP			OVL_DATAPATH_CON_FLD_OUTPUT_CLAMP
	#define DATAPATH_CON_FLD_OUTPUT_INTERLACE		OVL_DATAPATH_CON_FLD_OUTPUT_INTERLACE
	#define DATAPATH_CON_FLD_WIDE_GAMUT_EN			OVL_DATAPATH_CON_FLD_WIDE_GAMUT_EN


#define DISP_REG_OVL_ROI_BGCLR					DISP_OVL0_OVL_ROI_BGCLR
	#define ROI_BGCLR_FLD_BLUE						OVL_ROI_BGCLR_FLD_BLUE
	#define ROI_BGCLR_FLD_GREEN						OVL_ROI_BGCLR_FLD_GREEN
	#define ROI_BGCLR_FLD_RED						OVL_ROI_BGCLR_FLD_RED
	#define ROI_BGCLR_FLD_ALPHA						OVL_ROI_BGCLR_FLD_ALPHA

#define DISP_REG_OVL_SRC_CON					DISP_OVL0_OVL_SRC_CON
	#define SRC_CON_FLD_L0_EN						OVL_SRC_CON_FLD_L0_EN
	#define SRC_CON_FLD_L1_EN						OVL_SRC_CON_FLD_L1_EN
	#define SRC_CON_FLD_L2_EN						OVL_SRC_CON_FLD_L2_EN
	#define SRC_CON_FLD_L3_EN						OVL_SRC_CON_FLD_L3_EN
	#define SRC_CON_FLD_LC_EN						OVL_SRC_CON_FLD_LC_EN

#define DISP_REG_OVL_L0_CON						DISP_OVL0_OVL_L0_CON
	#define L_CON_FLD_APHA							OVL_L0_CON_FLD_ALPHA
	#define L_CON_FLD_AEN							OVL_L0_CON_FLD_ALPHA_EN
	#define L_CON_FLD_VIRTICAL_FLIP					OVL_L0_CON_FLD_VERTICAL_FLIP_EN
	#define L_CON_FLD_HORI_FLIP						OVL_L0_CON_FLD_HORIZONTAL_FLIP_EN
	#define L_CON_FLD_EXT_MTX_EN					OVL_L0_CON_FLD_EXT_MTX_EN
	#define L_CON_FLD_CFMT							OVL_L0_CON_FLD_CLRFMT
	#define L_CON_FLD_MTX							OVL_L0_CON_FLD_INT_MTX_SEL
	#define L_CON_FLD_BTSW							OVL_L0_CON_FLD_BYTE_SWAP
	#define L_CON_FLD_CLRFMT_MAN					OVL_L0_CON_FLD_CLRFMT_MAN
	#define L_CON_FLD_RGB_SWAP						OVL_L0_CON_FLD_RGB_SWAP
	#define L_CON_FLD_LARC							OVL_L0_CON_FLD_LAYER_SRC
	#define L_CON_FLD_SKEN							OVL_L0_CON_FLD_SRCKEY_EN

#define DISP_REG_OVL_L0_SRCKEY					DISP_OVL0_OVL_L0_SRCKEY
#define DISP_REG_OVL_L0_SRC_SIZE				DISP_OVL0_OVL_L0_SRC_SIZE
#define DISP_REG_OVL_L0_OFFSET					DISP_OVL0_OVL_L0_OFFSET
#define DISP_REG_OVL_L0_ADDR					DISP_OVL0_OVL_L0_ADDR
#define DISP_REG_OVL_L0_PITCH					DISP_OVL0_OVL_L0_PITCH
	#define L_PITCH_FLD_LSP							OVL_L0_PITCH_FLD_L0_SRC_PITCH
	#define L_PITCH_FLD_CONST_BLD					OVL_L0_PITCH_FLD_L0_CONST_BLD
	#define L_PITCH_FLD_SRGB_SEL					OVL_L0_PITCH_FLD_L0_SRGB_SEL
	#define L_PITCH_FLD_DRGB_SEL					OVL_L0_PITCH_FLD_L0_DRGB_SEL
	#define L_PITCH_FLD_SURFL_EN					OVL_L0_PITCH_FLD_SURFL_EN

#define DISP_REG_OVL_L0_TILE					DISP_OVL0_OVL_L0_TILE
#define DISP_REG_OVL_L0_CLIP					DISP_OVL0_OVL_L0_CLIP
	#define OVL_L_CLIP_FLD_LEFT						OVL_L0_CLIP_FLD_L0_SRC_LEFT_CLIP
	#define OVL_L_CLIP_FLD_RIGHT					OVL_L0_CLIP_FLD_L0_SRC_RIGHT_CLIP
	#define OVL_L_CLIP_FLD_TOP						OVL_L0_CLIP_FLD_L0_SRC_TOP_CLIP
	#define OVL_L_CLIP_FLD_BOTTOM					OVL_L0_CLIP_FLD_L0_SRC_BOTTOM_CLIP

#define DISP_REG_OVL_L1_CON						DISP_OVL0_OVL_L1_CON
#define DISP_REG_OVL_L1_SRCKEY					DISP_OVL0_OVL_L1_SRCKEY
#define DISP_REG_OVL_L1_SRC_SIZE				DISP_OVL0_OVL_L1_SRC_SIZE
#define DISP_REG_OVL_L1_OFFSET					DISP_OVL0_OVL_L1_OFFSET
#define DISP_REG_OVL_L1_ADDR					DISP_OVL0_OVL_L1_ADDR
#define DISP_REG_OVL_L1_PITCH					DISP_OVL0_OVL_L1_PITCH
#define DISP_REG_OVL_L1_TILE					DISP_OVL0_OVL_L1_TILE
#define DISP_REG_OVL_L1_CLIP					DISP_OVL0_OVL_L1_CLIP

#define DISP_REG_OVL_L2_CON						DISP_OVL0_OVL_L2_CON
#define DISP_REG_OVL_L2_SRCKEY					DISP_OVL0_OVL_L2_SRCKEY
#define DISP_REG_OVL_L2_SRC_SIZE				DISP_OVL0_OVL_L2_SRC_SIZE
#define DISP_REG_OVL_L2_OFFSET					DISP_OVL0_OVL_L2_OFFSET
#define DISP_REG_OVL_L2_ADDR					DISP_OVL0_OVL_L2_ADDR
#define DISP_REG_OVL_L2_PITCH					DISP_OVL0_OVL_L2_PITCH
#define DISP_REG_OVL_L2_TILE					DISP_OVL0_OVL_L2_TILE
#define DISP_REG_OVL_L2_CLIP					DISP_OVL0_OVL_L2_CLIP

#define DISP_REG_OVL_L3_CON						DISP_OVL0_OVL_L3_CON
#define DISP_REG_OVL_L3_SRCKEY					DISP_OVL0_OVL_L3_SRCKEY
#define DISP_REG_OVL_L3_SRC_SIZE				DISP_OVL0_OVL_L3_SRC_SIZE
#define DISP_REG_OVL_L3_OFFSET					DISP_OVL0_OVL_L3_OFFSET
#define DISP_REG_OVL_L3_ADDR					DISP_OVL0_OVL_L2_ADDR
#define DISP_REG_OVL_L3_PITCH					DISP_OVL0_OVL_L3_PITCH
#define DISP_REG_OVL_L3_TILE					DISP_OVL0_OVL_L3_TILE
#define DISP_REG_OVL_L3_CLIP					DISP_OVL0_OVL_L3_CLIP

#define DISP_REG_OVL_RDMA0_CTRL					DISP_OVL0_OVL_RDMA0_CTRL
	#define RDMA0_CTRL_FLD_RDMA_EN				OVL_RDMA0_CTRL_FLD_RDMA0_EN
	#define RDMA0_CTRL_FLD_RMDA_FIFO_USED_SZ	OVL_RDMA0_CTRL_FLD_RDMA0_FIFO_USED_SIZE

#define DISP_REG_OVL_RDMA0_MEM_GMC_SETTING				DISP_OVL0_OVL_RDMA0_MEM_GMC_SETTING1
	#define FLD_OVL_RDMA_MEM_GMC_ULTRA_THRESHOLD				OVL_RDMA0_MEM_GMC_SETTING1_FLD_RDMA0_ULTRA_THRESHOLD
	#define FLD_OVL_RDMA_MEM_GMC_PRE_ULTRA_THRESHOLD			OVL_RDMA0_MEM_GMC_SETTING1_FLD_RDMA0_PRE_ULTRA_THRESHOLD
	#define FLD_OVL_RDMA_MEM_GMC_ULTRA_THRESHOLD_HIGH_OFS		OVL_RDMA0_MEM_GMC_SETTING1_FLD_RDMA0_ULTRA_THRESHOLD_HIGH_OFS
	#define FLD_OVL_RDMA_MEM_GMC_PRE_ULTRA_THRESHOLD_HIGH_OFS	OVL_RDMA0_MEM_GMC_SETTING1_FLD_RDMA0_PRE_ULTRA_THRESHOLD_HIGH_OFS

#define DISP_REG_OVL_RDMA0_MEM_SLOW_CON				DISP_OVL0_OVL_RDMA0_MEM_SLOW_CON

#define DISP_REG_OVL_RDMA0_FIFO_CTRL				DISP_OVL0_OVL_RDMA0_FIFO_CTRL
	#define FLD_OVL_RDMA_FIFO_THRD						OVL_RDMA0_FIFO_CTRL_FLD_RDMA0_FIFO_THRD
	#define FLD_OVL_RDMA_FIFO_SIZE						OVL_RDMA0_FIFO_CTRL_FLD_RDMA0_FIFO_SIZE
	#define FLD_OVL_RDMA_FIFO_UND_EN					OVL_RDMA0_FIFO_CTRL_FLD_RDMA0_FIFO_UND_EN

#define DISP_REG_OVL_RDMA1_CTRL						DISP_OVL0_OVL_RDMA1_CTRL
#define DISP_REG_OVL_RDMA1_MEM_GMC_SETTING			DISP_OVL0_OVL_RDMA1_MEM_GMC_SETTING1
#define DISP_REG_OVL_RDMA1_MEM_SLOW_CON				DISP_OVL0_OVL_RDMA1_MEM_SLOW_CON
#define DISP_REG_OVL_RDMA1_FIFO_CTRL				DISP_OVL0_OVL_RDMA1_FIFO_CTRL
#define DISP_REG_OVL_RDMA2_CTRL						DISP_OVL0_OVL_RDMA2_CTRL
#define DISP_REG_OVL_RDMA2_MEM_GMC_SETTING			DISP_OVL0_OVL_RDMA2_MEM_GMC_SETTING1
#define DISP_REG_OVL_RDMA2_MEM_SLOW_CON				DISP_OVL0_OVL_RDMA2_MEM_SLOW_CON
#define DISP_REG_OVL_RDMA2_FIFO_CTRL				DISP_OVL0_OVL_RDMA2_FIFO_CTRL
#define DISP_REG_OVL_RDMA3_CTRL						DISP_OVL0_OVL_RDMA3_CTRL
#define DISP_REG_OVL_RDMA3_MEM_GMC_SETTING			DISP_OVL0_OVL_RDMA3_MEM_GMC_SETTING1
#define DISP_REG_OVL_RDMA3_MEM_SLOW_CON				DISP_OVL0_OVL_RDMA3_MEM_SLOW_CON
#define DISP_REG_OVL_RDMA3_FIFO_CTRL				DISP_OVL0_OVL_RDMA3_FIFO_CTRL

#define DISP_REG_OVL_L0_Y2R_PARA_R0					DISP_OVL0_OVL_L0_Y2R_PARA_R0
#define DISP_REG_OVL_L0_Y2R_PARA_R1					DISP_OVL0_OVL_L0_Y2R_PARA_R1
#define DISP_REG_OVL_L0_Y2R_PARA_G0					DISP_OVL0_OVL_L0_Y2R_PARA_G0
#define DISP_REG_OVL_L0_Y2R_PARA_G1					DISP_OVL0_OVL_L0_Y2R_PARA_G1
#define DISP_REG_OVL_L0_Y2R_PARA_B0					DISP_OVL0_OVL_L0_Y2R_PARA_B0
#define DISP_REG_OVL_L0_Y2R_PARA_B1					DISP_OVL0_OVL_L0_Y2R_PARA_B1)
#define DISP_REG_OVL_L0_Y2R_PARA_YUV_A_0			DISP_OVL0_OVL_L0_Y2R_PARA_YUV_A_0
#define DISP_REG_OVL_L0_Y2R_PARA_YUV_A_1			DISP_OVL0_OVL_L0_Y2R_PARA_YUV_A_1
#define DISP_REG_OVL_L0_Y2R_PARA_RGB_A_0			DISP_OVL0_OVL_L0_Y2R_PARA_RGB_A_0
#define DISP_REG_OVL_L0_Y2R_PARA_RGB_A_1			DISP_OVL0_OVL_L0_Y2R_PARA_RGB_A_1
#define DISP_REG_OVL_L1_Y2R_PARA_R0					DISP_OVL0_OVL_L1_Y2R_PARA_R0
#define DISP_REG_OVL_L1_Y2R_PARA_R1					DISP_OVL0_OVL_L1_Y2R_PARA_R1
#define DISP_REG_OVL_L1_Y2R_PARA_G0					DISP_OVL0_OVL_L1_Y2R_PARA_G0
#define DISP_REG_OVL_L1_Y2R_PARA_G1					DISP_OVL0_OVL_L1_Y2R_PARA_G1
#define DISP_REG_OVL_L1_Y2R_PARA_B0					DISP_OVL0_OVL_L1_Y2R_PARA_B0
#define DISP_REG_OVL_L1_Y2R_PARA_B1					DISP_OVL0_OVL_L1_Y2R_PARA_B1
#define DISP_REG_OVL_L1_Y2R_PARA_YUV_A_0			DISP_OVL0_OVL_L1_Y2R_PARA_YUV_A_0
#define DISP_REG_OVL_L1_Y2R_PARA_YUV_A_1			DISP_OVL0_OVL_L1_Y2R_PARA_YUV_A_1
#define DISP_REG_OVL_L1_Y2R_PARA_RGB_A_0			DISP_OVL0_OVL_L1_Y2R_PARA_RGB_A_0
#define DISP_REG_OVL_L1_Y2R_PARA_RGB_A_1			DISP_OVL0_OVL_L1_Y2R_PARA_RGB_A_1
#define DISP_REG_OVL_L2_Y2R_PARA_R0					DISP_OVL0_OVL_L2_Y2R_PARA_R0
#define DISP_REG_OVL_L2_Y2R_PARA_R1					DISP_OVL0_OVL_L2_Y2R_PARA_R1
#define DISP_REG_OVL_L2_Y2R_PARA_G0					DISP_OVL0_OVL_L2_Y2R_PARA_G0
#define DISP_REG_OVL_L2_Y2R_PARA_G1					DISP_OVL0_OVL_L2_Y2R_PARA_G1
#define DISP_REG_OVL_L2_Y2R_PARA_B0					DISP_OVL0_OVL_L2_Y2R_PARA_B0
#define DISP_REG_OVL_L2_Y2R_PARA_B1					DISP_OVL0_OVL_L2_Y2R_PARA_B1
#define DISP_REG_OVL_L2_Y2R_PARA_YUV_A_0			DISP_OVL0_OVL_L2_Y2R_PARA_YUV_A_0
#define DISP_REG_OVL_L2_Y2R_PARA_YUV_A_1			DISP_OVL0_OVL_L2_Y2R_PARA_YUV_A_1
#define DISP_REG_OVL_L2_Y2R_PARA_RGB_A_0			DISP_OVL0_OVL_L2_Y2R_PARA_RGB_A_0
#define DISP_REG_OVL_L2_Y2R_PARA_RGB_A_1			DISP_OVL0_OVL_L2_Y2R_PARA_RGB_A_1
#define DISP_REG_OVL_L3_Y2R_PARA_R0					DISP_OVL0_OVL_L3_Y2R_PARA_R0
#define DISP_REG_OVL_L3_Y2R_PARA_R1					DISP_OVL0_OVL_L3_Y2R_PARA_R1
#define DISP_REG_OVL_L3_Y2R_PARA_G0					DISP_OVL0_OVL_L3_Y2R_PARA_G0
#define DISP_REG_OVL_L3_Y2R_PARA_G1					DISP_OVL0_OVL_L3_Y2R_PARA_G1
#define DISP_REG_OVL_L3_Y2R_PARA_B0					DISP_OVL0_OVL_L3_Y2R_PARA_B0
#define DISP_REG_OVL_L3_Y2R_PARA_B1					DISP_OVL0_OVL_L3_Y2R_PARA_B1
#define DISP_REG_OVL_L3_Y2R_PARA_YUV_A_0			DISP_OVL0_OVL_L3_Y2R_PARA_YUV_A_0
#define DISP_REG_OVL_L3_Y2R_PARA_YUV_A_1			DISP_OVL0_OVL_L3_Y2R_PARA_YUV_A_1
#define DISP_REG_OVL_L3_Y2R_PARA_RGB_A_0			DISP_OVL0_OVL_L3_Y2R_PARA_RGB_A_0
#define DISP_REG_OVL_L3_Y2R_PARA_RGB_A_1			DISP_OVL0_OVL_L3_Y2R_PARA_RGB_A_1
#define DISP_REG_OVL_DEBUG_MON_SEL					DISP_OVL0_OVL_DEBUG_MON_SEL
#define DISP_REG_OVL_RDMA0_MEM_GMC_S2				DISP_OVL0_OVL_RDMA0_MEM_GMC_SETTING2
#define DISP_REG_OVL_RDMA1_MEM_GMC_S2				DISP_OVL0_OVL_RDMA1_MEM_GMC_SETTING2
#define DISP_REG_OVL_RDMA2_MEM_GMC_S2				DISP_OVL0_OVL_RDMA2_MEM_GMC_SETTING2
#define DISP_REG_OVL_RDMA3_MEM_GMC_S2				DISP_OVL0_OVL_RDMA3_MEM_GMC_SETTING2
#define DISP_REG_OVL_RDMA_BURST_CON0				DISP_OVL0_OVL_RDMA_BURST_CON0
#define DISP_REG_OVL_RDMA_BURST_CON1				DISP_OVL0_OVL_RDMA_BURST_CON1


#define DISP_REG_OVL_RDMA_GREQ_NUM					DISP_OVL0_OVL_RDMA_GREQ_NUM
	#define FLD_OVL_RDMA_GREQ_LAYER0_GREQ_NUM			OVL_RDMA_GREQ_NUM_FLD_LAYER0_GREQ_NUM
	#define FLD_OVL_RDMA_GREQ_LAYER1_GREQ_NUM			OVL_RDMA_GREQ_NUM_FLD_LAYER1_GREQ_NUM
	#define FLD_OVL_RDMA_GREQ_LAYER2_GREQ_NUM			OVL_RDMA_GREQ_NUM_FLD_LAYER2_GREQ_NUM
	#define FLD_OVL_RDMA_GREQ_LAYER3_GREQ_NUM			OVL_RDMA_GREQ_NUM_FLD_LAYER3_GREQ_NUM
	#define FLD_OVL_RDMA_GREQ_OSTD_GREQ_NUM				OVL_RDMA_GREQ_NUM_FLD_OSTD_GREQ_NUM
	#define FLD_OVL_RDMA_GREQ_GREQ_DIS_CNT				OVL_RDMA_GREQ_NUM_FLD_GREQ_DIS_CNT
	#define FLD_OVL_RDMA_GREQ_STOP_EN					OVL_RDMA_GREQ_NUM_FLD_GREQ_STOP_EN
	#define FLD_OVL_RDMA_GREQ_GRP_END_STOP				OVL_RDMA_GREQ_NUM_FLD_GRP_END_STOP
	#define FLD_OVL_RDMA_GREQ_GRP_BRK_STOP				OVL_RDMA_GREQ_NUM_FLD_GRP_BRK_STOP
	#define FLD_OVL_RDMA_GREQ_IOBUF_FLUSH_PREULTRA		OVL_RDMA_GREQ_NUM_FLD_IOBUF_FLUSH_PREULTRA
	#define FLD_OVL_RDMA_GREQ_IOBUF_FLUSH_ULTRA			OVL_RDMA_GREQ_NUM_FLD_IOBUF_FLUSH_ULTRA


#define DISP_REG_OVL_RDMA_GREQ_URG_NUM				DISP_OVL0_OVL_RDMA_GREQ_URG_NUM
	#define FLD_OVL_RDMA_GREQ_LAYER0_GREQ_URG_NUM		OVL_RDMA_GREQ_URG_NUM_FLD_LAYER0_GREQ_URG_NUM
	#define FLD_OVL_RDMA_GREQ_LAYER1_GREQ_URG_NUM		OVL_RDMA_GREQ_URG_NUM_FLD_LAYER1_GREQ_URG_NUM
	#define FLD_OVL_RDMA_GREQ_LAYER2_GREQ_URG_NUM		OVL_RDMA_GREQ_URG_NUM_FLD_LAYER2_GREQ_URG_NUM
	#define FLD_OVL_RDMA_GREQ_LAYER3_GREQ_URG_NUM		OVL_RDMA_GREQ_URG_NUM_FLD_LAYER3_GREQ_URG_NUM
	#define FLD_OVL_RDMA_GREQ_ARG_GREQ_URG_TH			OVL_RDMA_GREQ_URG_NUM_FLD_ARG_GREQ_URG_TH
	#define FLD_OVL_RDMA_GREQ_ARG_URG_BIAS				OVL_RDMA_GREQ_URG_NUM_FLD_ARG_URG_BIAS

#define DISP_REG_OVL_DUMMY_REG						DISP_OVL0_OVL_DUMMY_REG
#define DISP_REG_OVL_GDRDY_PRD						DISP_OVL0_OVL_GDRDY_PRD

#define DISP_REG_OVL_RDMA_ULTRA_SRC					DISP_OVL0_OVL_RDMA_ULTRA_SRC
	#define FLD_OVL_RDMA_PREULTRA_BUF_SRC				OVL_RDMA_ULTRA_SRC_FLD_PREULTRA_BUF_SRC
	#define FLD_OVL_RDMA_PREULTRA_SMI_SRC				OVL_RDMA_ULTRA_SRC_FLD_PREULTRA_SMI_SRC
	#define FLD_OVL_RDMA_PREULTRA_ROI_END_SRC			OVL_RDMA_ULTRA_SRC_FLD_PREULTRA_ROI_END_SRC
	#define FLD_OVL_RDMA_PREULTRA_RDMA_SRC				OVL_RDMA_ULTRA_SRC_FLD_PREULTRA_RDMA_SRC
	#define FLD_OVL_RDMA_ULTRA_BUF_SRC					OVL_RDMA_ULTRA_SRC_FLD_ULTRA_BUF_SRC
	#define FLD_OVL_RDMA_ULTRA_SMI_SRC					OVL_RDMA_ULTRA_SRC_FLD_ULTRA_SMI_SRC
	#define FLD_OVL_RDMA_ULTRA_ROI_END_SRC				OVL_RDMA_ULTRA_SRC_FLD_ULTRA_ROI_END_SRC
	#define FLD_OVL_RDMA_ULTRA_RDMA_SRC					OVL_RDMA_ULTRA_SRC_FLD_ULTRA_RDMA_SRC

#define DISP_REG_OVL_RDMAn_BUF_LOW(layer)			(DISP_OVL0_OVL_RDMA0_BUF_LOW + ((layer)<<2))
	#define FLD_OVL_RDMA_BUF_LOW_ULTRA_TH				OVL_RDMA0_BUF_LOW_FLD_BUF_LOW_ULTRA_TH
	#define FLD_OVL_RDMA_BUF_LOW_PREULTRA_TH			OVL_RDMA0_BUF_LOW_FLD_BUF_LOW_PREULTRA_TH
	
#define DISP_REG_OVL_RDMA0_BUF_LOW					DISP_OVL0_OVL_RDMA0_BUF_LOW
#define DISP_REG_OVL_RDMA1_BUF_LOW					DISP_OVL0_OVL_RDMA1_BUF_LOW
#define DISP_REG_OVL_RDMA2_BUF_LOW					DISP_OVL0_OVL_RDMA2_BUF_LOW
#define DISP_REG_OVL_RDMA3_BUF_LOW					DISP_OVL0_OVL_RDMA3_BUF_LOW
#define DISP_REG_OVL_SMI_DBG						DISP_OVL0_OVL_SMI_DBG
#define DISP_REG_OVL_GREQ_LAYER_CNT					DISP_OVL0_OVL_GREQ_LAYER_CNT
#define DISP_REG_OVL_GDRDY_PRD_NUM					DISP_OVL0_OVL_GDRDY_PRD_NUM
#define DISP_REG_OVL_FLOW_CTRL_DBG					DISP_OVL0_OVL_FLOW_CTRL_DBG
#define DISP_REG_OVL_ADDCON_DBG						DISP_OVL0_OVL_ADDCON_DBG
	#define ADDCON_DBG_FLD_ROI_X						OVL_ADDCON_DBG_FLD_ROI_X
	#define ADDCON_DBG_FLD_L0_WIN_HIT					OVL_ADDCON_DBG_FLD_L0_WIN_HIT
	#define ADDCON_DBG_FLD_L1_WIN_HIT					OVL_ADDCON_DBG_FLD_L1_WIN_HIT
	#define ADDCON_DBG_FLD_ROI_Y						OVL_ADDCON_DBG_FLD_ROI_Y
	#define ADDCON_DBG_FLD_L3_WIN_HIT					OVL_ADDCON_DBG_FLD_L3_WIN_HIT
	#define ADDCON_DBG_FLD_L2_WIN_HIT					OVL_ADDCON_DBG_FLD_L2_WIN_HIT
#define DISP_REG_OVL_RDMA0_DBG						DISP_OVL0_OVL_RDMA0_DBG
	#define RDMA0_DBG_FLD_RDMA0_WRAM_RST_CS				OVL_RDMA0_DBG_FLD_RDMA0_WRAM_RST_CS
	#define RDMA0_DBG_FLD_RDMA0_LAYER_GREQ         	 	OVL_RDMA0_DBG_FLD_RDMA0_LAYER_GREQ
	#define RDMA0_DBG_FLD_RDMA0_OUT_DATA				OVL_RDMA0_DBG_FLD_RDMA0_OUT_DATA
	#define RDMA0_DBG_FLD_RDMA0_OUT_READY				OVL_RDMA0_DBG_FLD_RDMA0_OUT_READY 
	#define RDMA0_DBG_FLD_RDMA0_OUT_VALID				OVL_RDMA0_DBG_FLD_RDMA0_OUT_VALID
	#define RDMA0_DBG_FLD_RDMA0_SMI_BUSY				OVL_RDMA0_DBG_FLD_RDMA0_SMI_BUSY
	#define RDMA0_DBG_FLD_RDMA0_SMI_GREQ				OVL_RDMA0_DBG_FLD_SMI_GREQ

#define DISP_REG_OVL_RDMA1_DBG						DISP_OVL0_OVL_RDMA1_DBG
#define DISP_REG_OVL_RDMA2_DBG						DISP_OVL0_OVL_RDMA2_DBG
#define DISP_REG_OVL_RDMA3_DBG						DISP_OVL0_OVL_RDMA3_DBG
#define DISP_REG_OVL_L0_CLR							DISP_OVL0_OVL_L0_CLR
#define DISP_REG_OVL_L1_CLR							DISP_OVL0_OVL_L1_CLR
#define DISP_REG_OVL_L2_CLR							DISP_OVL0_OVL_L2_CLR
#define DISP_REG_OVL_L3_CLR							DISP_OVL0_OVL_L3_CLR
#define DISP_REG_OVL_LC_CLR							DISP_OVL0_OVL_LC_CLR
#define DISP_REG_OVL_CRC							DISP_OVL0_OVL_CRC
#define DISP_REG_OVL_LC_CON							DISP_OVL0_OVL_LC_CON
#define DISP_REG_OVL_LC_SRCKEY						DISP_OVL0_OVL_LC_SRCKEY
#define DISP_REG_OVL_LC_SRC_SIZE					DISP_OVL0_OVL_LC_SRC_SIZE
#define DISP_REG_OVL_LC_OFFSET						DISP_OVL0_OVL_LC_OFFSET
#define DISP_REG_OVL_LC_SRC_SEL						DISP_OVL0_OVL_LC_SRC_SEL
#define DISP_REG_OVL_BANK_CON						DISP_OVL0_OVL_BANK_CON
#define DISP_REG_OVL_FUNC_DCM0						DISP_OVL0_OVL_FUNC_DCM0
#define DISP_REG_OVL_FUNC_DCM1						DISP_OVL0_OVL_FUNC_DCM1
#define DISP_REG_OVL_DVFS_L0_ROI					DISP_OVL0_OVL_DVFS_L0_ROI
#define DISP_REG_OVL_DVFS_L1_ROI					DISP_OVL0_OVL_DVFS_L1_ROI
#define DISP_REG_OVL_DVFS_L2_ROI					DISP_OVL0_OVL_DVFS_L2_ROI
#define DISP_REG_OVL_DVFS_L3_ROI					DISP_OVL0_OVL_DVFS_L3_ROI
#define DISP_REG_OVL_DVFS_EL0_ROI					DISP_OVL0_OVL_DVFS_EL0_ROI
#define DISP_REG_OVL_DVFS_EL1_ROI					DISP_OVL0_OVL_DVFS_EL1_ROI
#define DISP_REG_OVL_DVFS_EL2_ROI					DISP_OVL0_OVL_DVFS_EL2_ROI
#define DISP_REG_OVL_DATAPATH_EXT_CON				DISP_OVL0_OVL_DATAPATH_EXT_CON
#define DISP_REG_OVL_EL0_CON						DISP_OVL0_OVL_EL0_CON
#define DISP_REG_OVL_EL0_SRCKEY						DISP_OVL0_OVL_EL0_SRCKEY
#define DISP_REG_OVL_EL0_SRC_SIZE					DISP_OVL0_OVL_EL0_SRC_SIZE
#define DISP_REG_OVL_EL0_OFFSET						DISP_OVL0_OVL_EL0_OFFSET
#define DISP_REG_OVL_EL0_ADDR						DISP_OVL0_OVL_EL0_ADDR
#define DISP_REG_OVL_EL0_PITCH						DISP_OVL0_OVL_EL0_PITCH
#define DISP_REG_OVL_EL0_TILE						DISP_OVL0_OVL_EL0_TILE
#define DISP_REG_OVL_EL0_CLIP						DISP_OVL0_OVL_EL0_CLIP
#define DISP_REG_OVL_EL1_CON						DISP_OVL0_OVL_EL1_CON
#define DISP_REG_OVL_EL1_SRCKEY						DISP_OVL0_OVL_EL1_SRCKEY
#define DISP_REG_OVL_EL1_SRC_SIZE					DISP_OVL0_OVL_EL1_SRC_SIZE
#define DISP_REG_OVL_EL1_OFFSET						DISP_OVL0_OVL_EL1_OFFSET
#define DISP_REG_OVL_EL1_ADDR						DISP_OVL0_OVL_EL1_ADDR
#define DISP_REG_OVL_EL1_PITCH						DISP_OVL0_OVL_EL1_PITCH
#define DISP_REG_OVL_EL1_TILE						DISP_OVL0_OVL_EL1_TILE
#define DISP_REG_OVL_EL1_CLIP						DISP_OVL0_OVL_EL1_CLIP
#define DISP_REG_OVL_EL2_CON						DISP_OVL0_OVL_EL2_CON
#define DISP_REG_OVL_EL2_SRCKEY						DISP_OVL0_OVL_EL2_SRCKEY
#define DISP_REG_OVL_EL2_SRC_SIZE					DISP_OVL0_OVL_EL2_SRC_SIZE
#define DISP_REG_OVL_EL2_OFFSET						DISP_OVL0_OVL_EL2_OFFSET
#define DISP_REG_OVL_EL2_ADDR						DISP_OVL0_OVL_EL2_ADDR
#define DISP_REG_OVL_EL2_PITCH						DISP_OVL0_OVL_EL2_PITCH
#define DISP_REG_OVL_EL2_TILE						DISP_OVL0_OVL_EL2_TILE
#define DISP_REG_OVL_EL2_CLIP						DISP_OVL0_OVL_EL2_CLIP
#define DISP_REG_OVL_EL0_CLEAR						DISP_OVL0_OVL_EL0_CLR
#define DISP_REG_OVL_EL1_CLEAR						DISP_OVL0_OVL_EL1_CLR
#define DISP_REG_OVL_EL2_CLEAR						DISP_OVL0_OVL_EL2_CLR
#define DISP_REG_OVL_SECURE							DISP_OVL0_OVL_SECURE

#endif
